The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 14, 2020

Filed:

Jul. 18, 2018
Applicants:

International Business Machines Corporation, Armonk, NY (US);

Commissariat a L'energie Atomique ET Aux Energies Alternatives, Grenoble, FR;

Inventors:

Nicolas Loubet, Guilderland, NY (US);

Emmanuel Augendre, Le Sappey en Chartreuse, FR;

Remi Coquand, Le Touvet, FR;

Shay Reboh, La Buisse, FR;

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/8234 (2006.01); H01L 21/8238 (2006.01); H01L 29/66 (2006.01); H01L 29/06 (2006.01); H01L 29/78 (2006.01); H01L 29/423 (2006.01); H01L 27/088 (2006.01); H01L 21/3065 (2006.01); H01L 21/306 (2006.01);
U.S. Cl.
CPC ...
H01L 21/823431 (2013.01); H01L 21/823412 (2013.01); H01L 21/823842 (2013.01); H01L 27/0886 (2013.01); H01L 29/0673 (2013.01); H01L 29/42392 (2013.01); H01L 29/6653 (2013.01); H01L 29/6681 (2013.01); H01L 29/66553 (2013.01); H01L 29/7848 (2013.01); H01L 29/7853 (2013.01); H01L 21/3065 (2013.01); H01L 21/30604 (2013.01);
Abstract

Techniques for optimizing junctions of a gate-all-around nanosheet device are provided. In one aspect, a method of forming a nanosheet device includes: forming an alternating series of first/second nanosheets including a first/second material as a stack on a wafer; forming a dummy gate(s) on the stack; patterning the stack into a fin stack(s) beneath the dummy gate(s); etching the fin stack(s) to selectively pull back the second nanosheets in the fin stack(s) forming pockets in the fin stack(s); filling the pockets with a strain-inducing material; burying the dummy gate(s) in a dielectric material; selectively removing the dummy gate(s) forming a gate trench(es) in the dielectric material; selectively removing either the first nanosheets or the second nanosheets from the fin stack(s); and forming a replacement gate(s) in the gate trench(es). A nanosheet device is also provided.


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