The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 14, 2020

Filed:

Sep. 17, 2019
Applicant:

Ememory Technology Inc., Hsin-Chu, TW;

Inventors:

Chieh-Tse Lee, Hsinchu County, TW;

Chun-Hung Lin, Hsinchu County, TW;

Cheng-Da Huang, Hsinchu County, TW;

Assignee:

eMemory Technology Inc., Hsin-Chu, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 17/18 (2006.01); G11C 8/08 (2006.01); G11C 7/12 (2006.01); G11C 17/16 (2006.01); G11C 29/00 (2006.01); G11C 29/02 (2006.01);
U.S. Cl.
CPC ...
G11C 17/18 (2013.01); G11C 7/12 (2013.01); G11C 8/08 (2013.01); G11C 17/16 (2013.01); G11C 29/027 (2013.01); G11C 29/785 (2013.01);
Abstract

A memory system includes a plurality of memory cells. A memory cell includes an anti-fuse transistor, a first select unit, and a second select unit. The anti-fuse transistor has a first terminal, a second terminal, and a control terminal coupled to an anti-fuse control line. The first select unit is coupled to the first terminal of the anti-fuse transistor, a first bit line, and an odd word line. The second select unit is coupled to the second terminal of the anti-fuse transistor, a second bit line, and an even word line. During a pre-screen operation of the memory cell, the odd word line and the even word line are at different voltages.


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