The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jul. 07, 2020
Filed:
Apr. 28, 2017
Applicant:
Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu, TW;
Inventors:
Ka-Hing Fung, Zhudong Township, TW;
Chen-Yu Hsieh, Hsinchu, TW;
Che-Yuan Hsu, Hsinchu, TW;
Ming-Yuan Wu, Hsinchu, TW;
Hsu-Chieh Cheng, Hsinchu, TW;
Assignee:
TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., Hsinchu, TW;
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/66 (2006.01); H01L 21/66 (2006.01); H01L 29/78 (2006.01); H01L 27/088 (2006.01); H01L 21/8234 (2006.01);
U.S. Cl.
CPC ...
H01L 29/66795 (2013.01); H01L 21/823431 (2013.01); H01L 22/20 (2013.01); H01L 27/0886 (2013.01); H01L 29/66545 (2013.01); H01L 29/66818 (2013.01); H01L 29/785 (2013.01); H01L 29/7851 (2013.01); H01L 22/12 (2013.01); H01L 29/7848 (2013.01);
Abstract
A method includes forming a fin structure on a substrate, forming a dummy gate structure wrapped around the fin structure, depositing an Interlayer Dielectric (ILD) layer over the fin structure, removing the dummy gate structure to expose a portion of the fin structure, and performing an etching process on the portion of the fin structure to reduce a width of the portion of the fin structure.