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The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 10707221 B1

PDFFull Text
Date of Patent:
Jul. 07, 2020

Filed:

Oct. 24, 2018

Step coverage improvement for memory channel layer in 3d nand memory

Applicant:

Yangtze Memory Technologies Co., Ltd., Wuhan, Hubei, CN;

Inventors:

Er Wei Wang, Hubei, CN;

Yonggang Yang, Hubei, CN;

Assignee:

Yangtze Memory Technologies Co., Ltd., Wuhan, Hubei, CN;

Attorney:

Sterne, Kessler, Goldstein & Fox P.L.L.C.

Primary Examiner:

Vu A Vu

Int. Cl.
CPC ...
H01L 21/332 (2006.01); H01L 27/11556 (2017.01); H01L 27/11582 (2017.01); H01L 27/1157 (2017.01); H01L 21/3213 (2006.01); H01L 21/02 (2006.01);
U.S. Cl.
CPC ...
H01L 27/11556 (2013.01); H01L 21/0217 (2013.01); H01L 21/02164 (2013.01); H01L 21/02532 (2013.01); H01L 21/3213 (2013.01); H01L 27/1157 (2013.01); H01L 27/11582 (2013.01);
Abstract

Embodiments of an etching method for a material layer of a NAND memory device are disclosed. An example method of chemically etching a material layer on one or more substrates includes mixing an etchant solution within a bath and allowing the etchant solution to reach a quiescent state. After the etchant solution has reached the quiescent state, the method includes loading the one or more substrates into the bath. The one or more substrates includes a plurality of openings having the material layer disposed on an inside surface of the plurality of openings. The method also includes allowing the one or more substrates to remain in the bath for a predetermined time period, such that a thickness of the material layer is reduced by the etchant solution.

Find Patent Forward Citations

Wang, Er. (2020). Step coverage improvement for memory channel layer in 3d nand memory (U.S. Patent No. 10707221). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/10707221

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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