The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 07, 2020

Filed:

May. 24, 2018
Applicant:

International Business Machines Corporation, Armonk, NY (US);

Inventors:

Ricardo A. Donaton, Cortlandt Manor, NY (US);

Babar A. Khan, Ossining, NY (US);

Xinhui Wang, Poughkeepsie, NY (US);

Deepal Wehella-Gamage, Newburgh, NY (US);

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H01L 27/108 (2006.01); H01L 27/12 (2006.01); H01L 27/088 (2006.01); H01L 21/8234 (2006.01); H01L 21/02 (2006.01); H01L 21/033 (2006.01); H01L 21/306 (2006.01); H01L 29/66 (2006.01);
U.S. Cl.
CPC ...
H01L 27/10879 (2013.01); H01L 21/02181 (2013.01); H01L 21/02318 (2013.01); H01L 21/0337 (2013.01); H01L 21/30604 (2013.01); H01L 21/823431 (2013.01); H01L 27/0886 (2013.01); H01L 27/1087 (2013.01); H01L 27/10826 (2013.01); H01L 27/10832 (2013.01); H01L 27/10867 (2013.01); H01L 27/1211 (2013.01); H01L 29/66545 (2013.01);
Abstract

An integrated FinFET and deep trench capacitor structure and methods of manufacture are provided. The method includes forming deep trench capacitor structures in a silicon on insulator (SOI) wafer. The method further includes forming a plurality of composite fin structures from a semiconductor material of the SOI wafer and conductive material of the deep trench capacitor structures. The method further includes forming a liner over the deep trench capacitor structures including the conductive material of the deep trench capacitor structures. The method further includes forming replacement gate structures with the liner over the deep trench capacitor structures protecting the conductive material during deposition and etching processes.


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