The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 07, 2020

Filed:

Apr. 01, 2016
Applicant:

Intel Corporation, Santa Clara, CA (US);

Inventors:

Marko Radosavljevic, Portland, OR (US);

Sansaptak Dasgupta, Hillsboro, OR (US);

Valluri R. Rao, Saratoga, CA (US);

Han Wui Then, Portland, OR (US);

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/8258 (2006.01); H01L 29/778 (2006.01); H01L 29/78 (2006.01); H01L 27/092 (2006.01); H01L 29/06 (2006.01); H01L 29/66 (2006.01); H01L 29/04 (2006.01); H01L 21/762 (2006.01); H01L 27/06 (2006.01); H01L 29/20 (2006.01); H01L 29/423 (2006.01); H01L 29/417 (2006.01);
U.S. Cl.
CPC ...
H01L 21/8258 (2013.01); H01L 21/76224 (2013.01); H01L 27/0605 (2013.01); H01L 27/0924 (2013.01); H01L 29/045 (2013.01); H01L 29/0649 (2013.01); H01L 29/66462 (2013.01); H01L 29/7786 (2013.01); H01L 29/78 (2013.01); H01L 29/2003 (2013.01); H01L 29/41766 (2013.01); H01L 29/4236 (2013.01); H01L 29/7851 (2013.01);
Abstract

This disclosure is directed to a complementary metal oxide semiconductor (CMOS) transistor that includes a gallium nitride n-type MOS and a silicon P-type MOS. The transistor includes silicon 111 substrate, a gallium nitride transistor formed in a trench in the silicon 111 substrate, the gallium nitride transistor comprising a source electrode, a gate electrode, and a drain electrode; a polysilicon layer formed on the gallium nitride transistor, the polysilicon layer coplanar with a top side of the silicon 111 substrate; a first metal via disposed on the source electrode; a second metal via disposed on the gate electrode and isolated from the first metal via by a polysilicon layer; a first trench contact formed on the first metal via; and a second trench contact formed on the second metal via; the first trench contact isolated from the second trench contact by at least one replacement metal gate (RMG) polysilicon island.


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