The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 07, 2020

Filed:

Jun. 26, 2018
Applicant:

United Microelectronics Corp., Hsin-Chu, TW;

Inventors:

Chun-Yen Tseng, Tainan, TW;

Ching-Cheng Lung, Tainan, TW;

Yu-Tse Kuo, Tainan, TW;

Chun-Hsien Huang, Tainan, TW;

Hsin-Chih Yu, Hsinchu County, TW;

Shu-Ru Wang, Taichung, TW;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 11/00 (2006.01); G11C 11/412 (2006.01); G11C 11/419 (2006.01); H01L 43/08 (2006.01); G11C 7/12 (2006.01); H01L 27/11 (2006.01); H01L 43/02 (2006.01); H01L 43/10 (2006.01); G01R 33/09 (2006.01); G11C 8/08 (2006.01);
U.S. Cl.
CPC ...
G11C 11/412 (2013.01); G01R 33/091 (2013.01); G11C 7/12 (2013.01); G11C 8/08 (2013.01); G11C 11/419 (2013.01); H01L 27/1104 (2013.01); H01L 43/02 (2013.01); H01L 43/08 (2013.01); H01L 43/10 (2013.01);
Abstract

A static random access memory (SRAM) structure includes a first inverter comprising a first pull-up transistor and a first pull-down transistor, a second inverter comprising a second pull-up transistor and a second pull-down transistor, a first pass transistor coupled to the first inverter, and a second pass transistor coupled to the second inverter. Preferably, the first inverter is coupled to a first tunnel magnetoresistance (TMR) structure and the second inverter is coupled to a second TMR structure.


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