The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 30, 2020

Filed:

Nov. 14, 2017
Applicants:

Semiconductor Manufacturing International (Shanghai) Corporation, Shanghai, CN;

Semiconductor Manufacturing International (Beijing) Corporation, Beijing, CN;

Inventors:

Changzhou Wang, Shanghai, CN;

Jiquan Liu, Shanghai, CN;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 45/00 (2006.01); C23C 16/06 (2006.01); C23C 16/34 (2006.01);
U.S. Cl.
CPC ...
H01L 45/1683 (2013.01); C23C 16/06 (2013.01); C23C 16/34 (2013.01); H01L 45/04 (2013.01); H01L 45/06 (2013.01); H01L 45/10 (2013.01); H01L 45/1233 (2013.01); H01L 45/1253 (2013.01); H01L 45/16 (2013.01);
Abstract

The present disclosure discloses a resistive random access memory (RRAM) and a method for manufacture the RRAM. The method includes: providing a bottom interconnection layer; forming a bottom dielectric layer above the bottom interconnection layer, the bottom dielectric layer comprising a via through the bottom dielectric layer that exposes a portion of the bottom interconnection layer; and forming a bottom electrode layer in the via, the bottom electrode layer including a first electrode selectively grown above the bottom interconnection layer. The bottom electrode layer manufactured in such a way provides improved filling capability of the bottom electrode layer in the via.


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