The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 30, 2020

Filed:

Jul. 17, 2019
Applicant:

Ememory Technology Inc., Hsin-Chu, TW;

Inventors:

Chien-Han Wu, Hsinchu County, TW;

Chun-Hung Lu, Hsinchu County, TW;

Chun-Hung Lin, Hsinchu County, TW;

Cheng-Da Huang, Hsinchu County, TW;

Assignee:

eMemory Technology Inc., Hsin-Chu, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 7/00 (2006.01); H01L 27/11558 (2017.01); H03K 3/012 (2006.01); G11C 14/00 (2006.01); H01L 29/10 (2006.01); H01L 27/11524 (2017.01); G11C 16/04 (2006.01); G11C 16/14 (2006.01); G11C 16/26 (2006.01); G11C 16/10 (2006.01); H01L 29/49 (2006.01); H03K 19/0185 (2006.01); H03K 19/20 (2006.01); H03K 3/037 (2006.01); G11C 11/419 (2006.01); G11C 13/00 (2006.01); G11C 7/24 (2006.01); G11C 11/16 (2006.01); G11C 17/16 (2006.01);
U.S. Cl.
CPC ...
H01L 27/11558 (2013.01); G11C 7/24 (2013.01); G11C 11/165 (2013.01); G11C 11/419 (2013.01); G11C 13/0021 (2013.01); G11C 14/0054 (2013.01); G11C 16/0433 (2013.01); G11C 16/10 (2013.01); G11C 16/14 (2013.01); G11C 16/26 (2013.01); G11C 17/16 (2013.01); H01L 27/11524 (2013.01); H01L 29/1095 (2013.01); H01L 29/4916 (2013.01); H03K 3/012 (2013.01); H03K 3/037 (2013.01); H03K 19/018521 (2013.01); H03K 19/20 (2013.01);
Abstract

A random bit cell includes a random bit cell. The random bit cell includes a volatile memory unit, a first non-volatile memory unit, a second non-volatile memory unit, a first select transistor, and a second select transistor. The first non-volatile memory unit is coupled to a first data terminal of the volatile memory unit, and the second non-volatile memory unit is coupled to a second data terminal of the volatile memory unit. The first select transistor has a first terminal coupled to the first data terminal of the volatile memory unit, a second terminal coupled to a first bit line, and a control terminal coupled to a word line. The second select transistor has a first terminal coupled to the second data terminal of the volatile memory unit, a second terminal coupled to a second bit line, and a control terminal coupled to a word line.


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