The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 30, 2020

Filed:

Sep. 01, 2018
Applicant:

Intel Corporation, Santa Clara, CA (US);

Inventors:

Pratik J. Ashar, Mumbai, IN;

Supratim Pal, Bangalore, IN;

Subramaniam Maiyuran, Gold River, CA (US);

Wei-Yu Chen, San Jose, CA (US);

Guei-Yuan Lueh, San Jose, CA (US);

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 8/41 (2018.01); G06F 9/38 (2018.01); G06F 9/30 (2018.01); G06F 9/50 (2006.01);
U.S. Cl.
CPC ...
G06F 9/30101 (2013.01); G06F 8/441 (2013.01); G06F 9/30032 (2013.01); G06F 9/5016 (2013.01);
Abstract

An apparatus to facilitate register sharing is disclosed. The apparatus includes one or more processors to generate first machine code having a first General Purpose Register (GRF) per thread ratio, detect an occurrence of one or more spill/fill instructions in the first machine code, and generate second machine code having a second GRF per thread ratio upon a detection of one or more spill/fill instructions in the first machine code, wherein the second GRF per thread ratio is based on a disabling of a first of a plurality of hardware threads.


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