The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jun. 23, 2020
Filed:
Mar. 08, 2017
Semiconductor Manufacturing International (Shanghai) Corporation, Shanghai, CN;
Ningbo Semiconductor International Corporation, Ningbo, CN;
Herb He Huang, Shanghai, CN;
Clifford Ian Drowley, Shanghai, CN;
Jiguang Zhu, Shanghai, CN;
Haiting Li, Shanghai, CN;
Semiconductor Manufacturing International (Shanghai) Corporation, Shanghai, CN;
NINGBO SEMICONDUCTOR INTERNATIONAL CORPORATION, Ningbo, CN;
Abstract
A method for manufacturing a semiconductor apparatus includes: on a base substrate, forming an isolation trench layer, a first dielectric layer, a lower electrode layer and a second dielectric layer; forming a piezoelectric film and an upper electrode layer in an opening in the second dielectric layer; forming a third dielectric layer; forming a first cavity in the third dielectric layer to expose at least part of the upper electrode layer; bonding a first assistant substrate to seal the first cavity; removing a part of the base substrate to expose the isolation trench layer; forming a fourth dielectric layer on a side of the isolation trench; and etching through the fourth dielectric layer, the isolation trench layer, the first dielectric layer to form a second cavity beneath the lower electrode layer, plan views of the first and second cavities providing an overlapped region having a polygon shape without parallel sides.