The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jun. 23, 2020
Filed:
Jan. 04, 2019
Applicant:
International Business Machines Corporation, Armonk, NY (US);
Inventors:
Mark D. Jaffe, Shelburne, VT (US);
Alvin J. Joseph, Williston, VT (US);
Qizhi Liu, Lexington, MA (US);
Anthony K. Stamper, Burlington, VT (US);
Assignee:
INTERNATIONAL BUSINESS MACHINES CORPORATION, Armonk, NY (US);
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/02 (2006.01); H01L 21/762 (2006.01); H01L 29/06 (2006.01); H01L 29/78 (2006.01); H01L 29/66 (2006.01); H01L 21/265 (2006.01); H01L 21/764 (2006.01); H01L 21/306 (2006.01); H01L 29/786 (2006.01); H01L 27/12 (2006.01); H01L 21/027 (2006.01); H01L 21/266 (2006.01);
U.S. Cl.
CPC ...
H01L 21/76289 (2013.01); H01L 21/0273 (2013.01); H01L 21/02233 (2013.01); H01L 21/02238 (2013.01); H01L 21/266 (2013.01); H01L 21/26533 (2013.01); H01L 21/30604 (2013.01); H01L 21/764 (2013.01); H01L 21/76224 (2013.01); H01L 21/76283 (2013.01); H01L 21/76286 (2013.01); H01L 27/1207 (2013.01); H01L 29/0649 (2013.01); H01L 29/0653 (2013.01); H01L 29/66651 (2013.01); H01L 29/66757 (2013.01); H01L 29/66772 (2013.01); H01L 29/78 (2013.01); H01L 29/78603 (2013.01); H01L 29/78666 (2013.01); H01L 21/02255 (2013.01);
Abstract
A field effect transistor (FET) with an underlying airgap and methods of manufacture are disclosed. The method includes forming an amorphous layer at a predetermined depth of a substrate. The method further includes forming an airgap in the substrate under the amorphous layer. The method further includes forming a completely isolated transistor in an active region of the substrate, above the amorphous layer and the airgap.