The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 16, 2020

Filed:

Jan. 26, 2017
Applicants:

Semiconductor Manufacturing International (Shanghai) Corporation, Shanghai, CN;

Ningbo Semiconductor International Corporation, Ningbo, CN;

Inventors:

Herb He Huang, Shanghai, CN;

Clifford Ian Drowley, Shanghai, CN;

Jiguang Zhu, Shanghai, CN;

Haiting Li, Shanghai, CN;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03H 3/02 (2006.01); H03H 9/17 (2006.01); H03H 9/05 (2006.01); H03H 9/58 (2006.01); H01L 27/20 (2006.01); H03H 3/007 (2006.01); H03H 9/02 (2006.01); H03H 9/15 (2006.01);
U.S. Cl.
CPC ...
H03H 3/02 (2013.01); H01L 27/20 (2013.01); H03H 3/0073 (2013.01); H03H 9/02007 (2013.01); H03H 9/0547 (2013.01); H03H 9/171 (2013.01); H03H 9/173 (2013.01); H03H 9/587 (2013.01); H03H 2003/021 (2013.01); H03H 2003/027 (2013.01); H03H 2009/155 (2013.01); Y10T 29/42 (2015.01); Y10T 29/49005 (2015.01);
Abstract

A method for manufacturing a semiconductor apparatus includes: on a base substrate, forming an isolation trench layer, a first dielectric layer, a first metal connecting layer, a piezoelectric film, and an upper electrode layer; forming an acoustic resonance film by patternizing the piezoelectric film, the upper electrode layer, and the first metal connecting layer; above the base substrate, forming a second dielectric layer and a third dielectric layer; forming a first cavity through the third and second dielectric layers, and the protection layer; removing a part of the base substrate to expose the isolation trench layer; forming a fourth dielectric layer under the isolation trench layer; and forming a second cavity through the fourth dielectric layer, the isolation trench layer, and the first dielectric layer, plan views of the first and second cavities forming an overlapped region having a polygon shape without parallel sides.


Find Patent Forward Citations

Loading…