The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 16, 2020

Filed:

Aug. 16, 2019
Applicants:

Semiconductor Manufacturing International (Beijing) Corporation, Beijing, CN;

Semiconductor Manufacturing International (Shanghai) Corporation, Shanghai, CN;

Inventors:

Ji Shiliang, Shanghai, CN;

Zhang Yiying, Shanghai, CN;

Zhang Haiyang, Shanghai, CN;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/033 (2006.01); H01L 27/088 (2006.01); H01L 29/10 (2006.01); H01L 21/8234 (2006.01); H01L 21/027 (2006.01);
U.S. Cl.
CPC ...
H01L 21/0338 (2013.01); H01L 21/0276 (2013.01); H01L 21/0332 (2013.01); H01L 21/0335 (2013.01); H01L 21/0337 (2013.01); H01L 21/823412 (2013.01); H01L 21/823431 (2013.01); H01L 27/0886 (2013.01); H01L 29/1037 (2013.01);
Abstract

Disclosed are a semiconductor structure and a method for forming the same. The method includes: providing a base, including a first region and a second region, where a pitch between target patterns formed on the first region is greater than a pitch between target patterns formed on the second region; forming a bottom core material layer on the base; forming first core layers on the bottom core material layer; forming a first mask sidewall on a sidewall of the first core layer of the first region, and forming a second mask sidewall on a sidewall of the first core layer of the second region, where the thickness of the second mask sidewall is greater than the thickness of the first mask sidewall; removing the first core layers; patterning the bottom core material layer by using the first mask sidewall and the second mask sidewall as masks, to form a second core layer; removing the first mask sidewall and the second mask sidewall; forming a third mask sidewall on a sidewall of the second core layer; removing the second core layer; and patterning the base by using the third mask sidewall as a mask, to form target patterns protruding out of a residual base. The present disclosure meets the requirement of different pitches of the target patterns.


Find Patent Forward Citations

Shiliang, Ji. (2020). Semiconductor structure providing for an increased pattern density on a substrate and method for forming same (U.S. Patent No. 10685838). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/10685838

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

Loading…