The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jun. 16, 2020
Filed:
Sep. 12, 2018
Nxp B.v., Eindhoven, NL;
Jainendra Singh, Bangalore, IN;
Sushikha Jain, Uttar Pradesh, IN;
Deepti Saini, Bangalore, IN;
Jwalant Kumar Mishra, Bangalore, IN;
Patrick Van de Steeg, Oss, NL;
NXP B.V., San Jose, CA (US);
Abstract
A semiconductor memory circuit includes a SRAM cell and a bias control circuit for biasing the SRAM cell. The SRAM cell includes pull-up, pull-down, and pass-gate transistors. The bias control circuit is connected to body terminals of the pull-down and pass-gate transistors for providing a bias voltage. The bias control circuit controls threshold voltages of the pull-down and pass-gate transistors by way of the bias voltage. The bias voltage, which is temperature dependent, is generated based on junction leakages at the body terminals of the pull-down and pass-gate transistors. The use of a temperature-dependent bias voltage to bias the body terminals of the pull-down and pass-gate transistors ensures that the write margin and the static noise margin (SNM) of the SRAM cell are relatively constant and above acceptable levels over a defined temperature range.