The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 09, 2020

Filed:

Oct. 17, 2017
Applicant:

Globalfoundries Inc., Grand Cayman, KY;

Inventors:

Xunyuan Zhang, Albany, NY (US);

Frank W. Mont, Troy, NY (US);

Errol Todd Ryan, Clifton Park, NY (US);

Assignee:

GLOBALFOUNDRIES INC., Grand Cayman, KY;

Attorneys:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 23/522 (2006.01); H01L 23/532 (2006.01); H01L 21/02 (2006.01); H01L 21/285 (2006.01); H01L 21/768 (2006.01); H01L 23/528 (2006.01);
U.S. Cl.
CPC ...
H01L 23/5226 (2013.01); H01L 21/02244 (2013.01); H01L 21/2855 (2013.01); H01L 21/28556 (2013.01); H01L 21/28568 (2013.01); H01L 21/7682 (2013.01); H01L 21/7684 (2013.01); H01L 21/7685 (2013.01); H01L 21/76856 (2013.01); H01L 21/76864 (2013.01); H01L 23/528 (2013.01); H01L 23/53252 (2013.01); H01L 23/53295 (2013.01); H01L 21/76834 (2013.01); H01L 21/76865 (2013.01); H01L 23/5222 (2013.01);
Abstract

Devices and methods of fabricating integrated circuit devices for forming low resistivity interconnects are provided. One method includes, for instance: obtaining an intermediate semiconductor interconnect device having a substrate, a cap layer, and a dielectric matrix including a set of trenches and a set of vias; depositing a barrier layer along a top surface of the semiconductor interconnect device; depositing and annealing a metal interconnect material over a top surface of the barrier layer, wherein the metal interconnect material fills the set of trenches and the set of vias; planarizing a top surface of the intermediate semiconductor interconnect device; exposing a portion of the barrier layer between the set of trenches and the set of vias; and depositing a dielectric cap. Also disclosed is an intermediate device formed by the method.


Find Patent Forward Citations

Loading…