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The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 10679891 B1

PDFFull Text
Date of Patent:
Jun. 09, 2020

Filed:

Feb. 01, 2018

Methods of forming interconnect structures using a vacuum environment

Applicant:

Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu, TW;

Inventors:

Chia-Ching Tsai, Tainan, TW;

Yi-Wei Chiu, Kaohsiung, TW;

Hung Jui Chang, Shetou Shiang, TW;

Li-Te Hsu, Shanhua Township, TW;

Assignee:

Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu, TW;

Attorney:

Slater Matsil, LLP

Primary Examiner:

Caleb E Henry

Int. Cl.
CPC ...
H01L 21/44 (2006.01); H01L 21/768 (2006.01); H01L 21/8238 (2006.01); H01L 27/092 (2006.01); H01L 29/78 (2006.01); H01L 29/66 (2006.01); H01L 23/532 (2006.01); H01L 23/522 (2006.01);
U.S. Cl.
CPC ...
H01L 21/76807 (2013.01); H01L 21/7684 (2013.01); H01L 21/76811 (2013.01); H01L 21/76813 (2013.01); H01L 21/76816 (2013.01); H01L 21/76832 (2013.01); H01L 21/76843 (2013.01); H01L 21/76873 (2013.01); H01L 21/823821 (2013.01); H01L 27/0924 (2013.01); H01L 29/66545 (2013.01); H01L 29/785 (2013.01); H01L 29/7853 (2013.01); H01L 21/76862 (2013.01); H01L 23/5226 (2013.01); H01L 23/53238 (2013.01); H01L 29/7848 (2013.01);
Abstract

An interconnect structure and a method of forming are provided. The method includes forming an opening in a dielectric layer and an etch stop layer, wherein the opening extends only partially through the etch stop layer. The method also includes creating a vacuum environment around the device. After creating the vacuum environment around the device, the method includes etching through the etch stop layer to extend the opening and expose a first conductive feature. The method also includes forming a second conductive feature in the opening.

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