The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jun. 09, 2020
Filed:
Mar. 01, 2017
Intel Corporation, Santa Clara, CA (US);
Abram M. Detofsky, Tigard, OR (US);
Evan M. Fledell, Hillsboro, OR (US);
Mustapha A. Abdulai, Hillsboro, OR (US);
John M. Peterson, Hillsboro, OR (US);
Dinia P. Kitendaugh, Beaverton, OR (US);
Pooya Tadayon, Portland, OR (US);
Jin Pan, Portland, OR (US);
David Shia, Hillsboro, OR (US);
Intel Corporation, Santa Clara, CA (US);
Abstract
A testing system and process comprises a converged test platform for structural testing and system testing of an integrated circuit device. The testing system comprises a converged test platform supported by a baseboard of an automated test assembly. The converged test platform comprises a DUT socket for testing an integrated circuit device, at least one testing electronic component selectively electrically coupled to the DUT socket by at least one switch operable to electrically switch at least some testing signals between the automated testing assembly and the DUT socket to the at least one testing electronic component for both structural testing and system testing of the integrated circuit device within the same test flow. The switch(es) and testing electronic component(s) (e.g., an FPGA) can be reprogrammable for testing flexibility and faster through put. Associated processes and methods are provided for both class and system testing using the converged test platform for back-end and front-end testing.