The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 09, 2020

Filed:

May. 11, 2015
Applicants:

Tamura Corporation, Tokyo, JP;

National University Corporation Tokyo University of Agriculture and Technology, Tokyo, JP;

Inventors:

Ken Goto, Tokyo, JP;

Akinori Koukitu, Tokyo, JP;

Yoshinao Kumagai, Fuchu, JP;

Hisashi Murakami, Fuchu, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
C30B 25/20 (2006.01); C30B 29/16 (2006.01); H01L 21/205 (2006.01); C23C 16/44 (2006.01); H01L 21/02 (2006.01); H01L 29/04 (2006.01); H01L 29/24 (2006.01);
U.S. Cl.
CPC ...
C30B 25/20 (2013.01); C23C 16/44 (2013.01); C30B 29/16 (2013.01); H01L 21/0262 (2013.01); H01L 21/02414 (2013.01); H01L 21/02428 (2013.01); H01L 21/02433 (2013.01); H01L 21/02565 (2013.01); H01L 21/02598 (2013.01); H01L 21/02634 (2013.01); H01L 21/205 (2013.01); H01L 29/045 (2013.01); H01L 29/24 (2013.01);
Abstract

A semiconductor substrate for being used as a base substrate for epitaxial crystal growth by HVPE method includes a β-GaO-based single crystal, and a principal surface that is a plane parallel to a [010] axis of the β-GaO-based single crystal. An epitaxial wafer includes the semiconductor substrate, and an epitaxial layer that includes a β-GaO-based single crystal and is formed on the principal surface of the semiconductor substrate by epitaxial crystal growth using the HVPE method. A method for manufacturing the epitaxial wafer includes forming the epitaxial layer by epitaxial crystal growth using the HVPE method on the semiconductor substrate.


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