The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 02, 2020

Filed:

Aug. 08, 2019
Applicants:

Semiconductor Manufacturing International (Shanghai) Corporation, Shanghai, CN;

Semiconductor Manufacturing International (Beijing) Corporation, Beijing, CN;

Inventors:

Jiaqi Yang, Shanghai, CN;

Jie Zhao, Shanghai, CN;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 27/06 (2006.01); H01L 21/306 (2006.01); H01L 21/8238 (2006.01); H01L 27/092 (2006.01); H01L 29/49 (2006.01); H01L 49/02 (2006.01); H01L 21/3065 (2006.01); H01L 29/51 (2006.01); H01L 21/28 (2006.01); H01L 29/66 (2006.01);
U.S. Cl.
CPC ...
H01L 21/823842 (2013.01); H01L 21/28088 (2013.01); H01L 21/3065 (2013.01); H01L 21/30604 (2013.01); H01L 27/0629 (2013.01); H01L 27/092 (2013.01); H01L 28/20 (2013.01); H01L 29/4966 (2013.01); H01L 29/517 (2013.01); H01L 29/66545 (2013.01);
Abstract

A semiconductor device includes a semiconductor substrate, an interlayer dielectric layer on the semiconductor substrate, a plurality of trenches extending through the interlayer dielectric layer to the semiconductor substrate and comprising a first trench of a PMOS device and a second trench of an NMOS device, a high-k dielectric layer on a bottom and sidewalls of the trenches, a PMOS work function adjustment layer on the high-k dielectric layer in the first trench, an NMOS work function adjustment layer on the high-k dielectric layer in the second trench, and a metal electrode layer on the PMOS work function adjustment layer in the first trench and on the NMOS work function adjustment layer in the second trench.


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