The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 02, 2020

Filed:

Aug. 28, 2018
Applicant:

Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu, TW;

Inventors:

Shu-Uei Jang, Hsinchu, TW;

Chien-Hua Tseng, Hsinchu, TW;

Chung-Shu Wu, Taoyuan, TW;

Ya-Yi Tsai, Hsinchu, TW;

Ryan Chia-Jen Chen, Chiayi, TW;

An-Chyi Wei, Hsinchu, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/28 (2006.01); H01L 21/3105 (2006.01); H01L 21/311 (2006.01); H01L 21/3213 (2006.01); H01L 29/78 (2006.01); H01L 21/02 (2006.01); H01L 21/762 (2006.01); H01L 29/66 (2006.01); H01L 29/06 (2006.01);
U.S. Cl.
CPC ...
H01L 21/28123 (2013.01); H01L 21/02156 (2013.01); H01L 21/02186 (2013.01); H01L 21/31055 (2013.01); H01L 21/31111 (2013.01); H01L 21/31116 (2013.01); H01L 21/32133 (2013.01); H01L 21/32139 (2013.01); H01L 21/76224 (2013.01); H01L 29/0653 (2013.01); H01L 29/66795 (2013.01); H01L 29/7851 (2013.01); H01L 29/66545 (2013.01);
Abstract

A method of forming a semiconductor structure includes forming a metal gate stack over a shallow trench isolation (STI) material in a semiconductor substrate, forming an interlayer dielectric over the STI material, recessing the interlayer dielectric to a height lower than a top surface of the metal gate stack, forming a helmet structure over the recessed interlayer dielectric, and after forming the helmet structure, etching the metal gate stack until reaching the STI material.


Find Patent Forward Citations

Loading…