The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 19, 2020

Filed:

Jul. 02, 2016
Applicant:

Intel Corporation, Santa Clara, CA (US);

Inventors:

James S. Clarke, Portland, OR (US);

Ravi Pillarisetty, Portland, OR (US);

Uday Shah, Portland, OR (US);

Tejaswi K. Indukuri, Portland, OR (US);

Niloy Mukherjee, Portland, OR (US);

Elijah V. Karpov, Portland, OR (US);

Prashant Majhi, San Jose, CA (US);

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 45/00 (2006.01); H01L 27/24 (2006.01); G11C 13/00 (2006.01);
U.S. Cl.
CPC ...
H01L 45/146 (2013.01); H01L 27/2436 (2013.01); H01L 27/2463 (2013.01); H01L 45/085 (2013.01); H01L 45/1233 (2013.01); H01L 45/1253 (2013.01); H01L 45/1266 (2013.01); H01L 45/1625 (2013.01); H01L 45/1633 (2013.01); H01L 45/1675 (2013.01); G11C 13/0007 (2013.01);
Abstract

Embodiments of the present invention include RRAM devices and their methods of fabrication. In an embodiment, a resistive random access memory (RRAM) cell includes a conductive interconnect disposed in a dielectric layer above a substrate. An RRAM device is coupled to the conductive interconnect. An RRAM memory includes a bottom electrode disposed above the conductive interconnect and on a portion of the dielectric layer. A conductive layer is formed on the bottom electrode layer. The conductive layer is separate and distinct from the bottom electrode layer. The conductive layer further includes a material that is different from the bottom electrode layer. A switching layer is formed on the conductive layer. An oxygen exchange layer is formed on the switching layer and a top electrode is formed on the oxygen exchange layer.


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