The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
May. 19, 2020
Filed:
Oct. 30, 2018
Applicant:
Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu, TW;
Inventors:
Fu-Hsiang Su, Hsinchu, TW;
Jyh-Huei Chen, Hsinchu, TW;
Kuo-Chiang Tsai, Hsinchu, TW;
Ke-Jing Yu, Kaohsiung, TW;
Assignee:
Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu, TW;
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/06 (2006.01); H01L 21/768 (2006.01); H01L 27/092 (2006.01); H01L 23/535 (2006.01); H01L 21/033 (2006.01); H01L 21/8238 (2006.01);
U.S. Cl.
CPC ...
H01L 21/76897 (2013.01); H01L 21/0332 (2013.01); H01L 21/0335 (2013.01); H01L 21/823821 (2013.01); H01L 21/823871 (2013.01); H01L 23/535 (2013.01); H01L 27/0924 (2013.01);
Abstract
Semiconductor devices are provided, and includes a substrate, a first gate structure and a second gate structure over the substrate, a first hard mask on the first gate structure and a second hard mask on the second gate structure and a third hard mask. The third hard mask is disposed in a dielectric layer between the first gate structure and the second gate structure and disposed between the first hard mask and the second hard mask.