The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
May. 12, 2020
Filed:
Jan. 03, 2019
Applicant:
United Microelectronics Corp., Hsin-Chu, TW;
Inventors:
Assignee:
UNITED MICROELECTRONICS CORP., Hsin-Chu, TW;
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/66 (2006.01); H01L 21/3105 (2006.01); H01L 21/3115 (2006.01); H01L 21/02 (2006.01); H01L 21/768 (2006.01); H01L 29/417 (2006.01); H01L 29/51 (2006.01); H01L 29/49 (2006.01); H01L 29/78 (2006.01);
U.S. Cl.
CPC ...
H01L 29/66545 (2013.01); H01L 21/02326 (2013.01); H01L 21/02337 (2013.01); H01L 21/02348 (2013.01); H01L 21/3115 (2013.01); H01L 21/31053 (2013.01); H01L 21/76826 (2013.01); H01L 21/76828 (2013.01); H01L 21/76834 (2013.01); H01L 29/6656 (2013.01); H01L 29/66575 (2013.01); H01L 29/66795 (2013.01); H01L 21/76825 (2013.01); H01L 29/41791 (2013.01); H01L 29/4966 (2013.01); H01L 29/517 (2013.01); H01L 29/785 (2013.01);
Abstract
A method for fabricating semiconductor device includes the steps of first forming a gate structure on a substrate, forming a contact etch stop layer (CESL) on the gate structure, forming an interlayer dielectric (ILD) layer around the gate structure, performing a curing process so that an oxygen concentration of the CESL is different from the oxygen concentration of the ILD layer, and then performing a replacement metal gate process (RMG) process to transform the gate structure into a metal gate.