The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
May. 05, 2020
Filed:
Jul. 03, 2019
Applicant:
United Microelectronics Corp., Hsin-Chu, TW;
Inventors:
Yen-Hsing Chen, Taipei, TW;
Chun-Yu Chen, Taichung, TW;
Chung-Ting Huang, Kaohsiung, TW;
Zih-Hsuan Huang, Tainan, TW;
Yu-Chien Sung, Taoyuan, TW;
Assignee:
UNITED MICROELECTRONICS CORP., Hsin-Chu, TW;
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/66 (2006.01); H01L 21/3213 (2006.01); H01L 29/06 (2006.01); H01L 21/033 (2006.01); H01L 29/78 (2006.01); H01L 27/088 (2006.01); H01L 29/10 (2006.01);
U.S. Cl.
CPC ...
H01L 29/66636 (2013.01); H01L 21/033 (2013.01); H01L 21/32139 (2013.01); H01L 27/0886 (2013.01); H01L 29/0653 (2013.01); H01L 29/1054 (2013.01); H01L 29/6656 (2013.01); H01L 29/66545 (2013.01); H01L 29/66795 (2013.01); H01L 29/66818 (2013.01); H01L 29/7848 (2013.01);
Abstract
A method for fabricating a semiconductor device is disclosed. A fin is formed on a substrate. The fin protrudes from a trench isolation layer on a substrate. The fin comprises a source region, a drain region and a channel region therebetween. A dummy gate strides across the fin and surrounding the channel region. An upper portion of the fin is removed so as to form a hollow channel underneath the dummy gate. A replacement channel layer is in-situ epitaxially grown in the hollow channel.