The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 05, 2020

Filed:

Oct. 11, 2019
Applicant:

International Business Machines Corporation, Armonk, NY (US);

Inventors:

Ruqiang Bao, Niskayuna, NY (US);

Siva Kanakasabapathy, Pleasanton, CA (US);

Andrew M. Greene, Albany, NY (US);

Attorneys:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 27/088 (2006.01); H01L 21/8234 (2006.01); H01L 21/8238 (2006.01); H01L 29/78 (2006.01); H01L 29/66 (2006.01); H01L 21/768 (2006.01); H01L 21/027 (2006.01); H01L 21/306 (2006.01); H01L 21/308 (2006.01); H01L 21/762 (2006.01);
U.S. Cl.
CPC ...
H01L 29/66545 (2013.01); H01L 21/0276 (2013.01); H01L 21/3081 (2013.01); H01L 21/30604 (2013.01); H01L 21/76224 (2013.01); H01L 21/76843 (2013.01); H01L 21/76885 (2013.01); H01L 21/823431 (2013.01); H01L 21/823821 (2013.01); H01L 21/823842 (2013.01); H01L 27/0886 (2013.01); H01L 29/66795 (2013.01); H01L 29/785 (2013.01);
Abstract

A method is presented for performing a gate cut in a field effect transistor (FET) structure. The method includes forming a plurality of fins and at least one insulating pillar over a semiconductor substrate, depositing a first work function metal layer, removing the first work function metal layer from a first set of fins, depositing a second work function metal layer, depositing a conductive material over the second work function metal layer, forming at least one gate trench through the conductive material and adjacent the first set of fins to separate active gate regions, and filling the at least one gate trench with an insulating material.


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