The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 05, 2020

Filed:

Dec. 15, 2017
Applicant:

Micron Technology, Inc., Boise, ID (US);

Inventors:

David K. Hwang, Boise, ID (US);

John A. Smythe, Boise, ID (US);

Haitao Liu, Boise, ID (US);

Richard J. Hill, Boise, ID (US);

Deepak Chandra Pandey, Boise, ID (US);

Assignee:

Micron Technology, Inc., Boise, ID (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/8239 (2006.01); H01L 21/8234 (2006.01); H01L 29/10 (2006.01); G11C 11/40 (2006.01); H01L 27/108 (2006.01); H01L 21/8229 (2006.01);
U.S. Cl.
CPC ...
H01L 21/8239 (2013.01); G11C 11/40 (2013.01); H01L 21/8229 (2013.01); H01L 21/823437 (2013.01); H01L 21/823462 (2013.01); H01L 27/10885 (2013.01); H01L 27/10888 (2013.01); H01L 27/10891 (2013.01); H01L 29/105 (2013.01); G11C 2211/4016 (2013.01); H01L 21/823418 (2013.01);
Abstract

An embodiment of the invention comprises a method of forming a transistor comprising forming a gate construction having an elevationally-outermost surface of conductive gate material that is lower than an elevationally-outer surface of semiconductor material that is aside and above both sides of the gate construction. Tops of the semiconductor material and the conductive gate material are covered with masking material, two pairs of two opposing sidewall surfaces of the semiconductor material are laterally exposed above both of the sides of the gate construction. After the covering, the semiconductor material that is above both of the sides of the gate construction is subjected to monolayer doping through each of the laterally-exposed two opposing sidewall surfaces of each of the two pairs and forming there-from doped source/drain regions above both of the sides of the gate construction.


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