The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 28, 2020

Filed:

Feb. 21, 2019
Applicant:

Winbond Electronics Corp., Taichung, TW;

Inventors:

Chia-Wen Cheng, Hsinchu, TW;

Yi-Hsiu Chen, Zhubei, TW;

Po-Yen Hsu, New Taipei, TW;

Ping-Kun Wang, Tianzhong Township, Changhua County, TW;

Ming-Che Lin, Taichung, TW;

He-Hsuan Chao, Hsinchu, TW;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 27/24 (2006.01); H01L 45/00 (2006.01);
U.S. Cl.
CPC ...
H01L 27/2463 (2013.01); H01L 27/2436 (2013.01); H01L 45/08 (2013.01); H01L 45/1233 (2013.01); H01L 45/1246 (2013.01); H01L 45/1253 (2013.01); H01L 45/146 (2013.01); H01L 45/1625 (2013.01); H01L 45/1675 (2013.01);
Abstract

A method for forming a resistive random access memory includes forming a layer stack, patterning the layer stack to form a plurality of stack structures, forming a protection layer along sidewalls of the plurality of stack structures, forming a first isolation structure between the plurality of stack structures, forming at least one recess in at least one stack structure to define a plurality of filament units, and forming a second isolation structure in the at least one recess. The layer stack includes a bottom electrode and a resistive switching layer on the bottom electrode.


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