The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Apr. 28, 2020
Filed:
Mar. 30, 2018
Applicant:
Samsung Electronics Co., Ltd., Suwon-si, KR;
Inventors:
Kyung Hwan Lee, Hwaseong-si, KR;
Yong Seok Kim, Suwon-si, KR;
Tae Hun Kim, Gwacheon-si, KR;
Byoung Taek Kim, Hwaseong-si, KR;
Jun Hee Lim, Seoul, KR;
Assignee:
SAMSUNG ELECTRONICS CO., LTD., Suwon-si, KR;
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 27/11582 (2017.01); H01L 29/423 (2006.01); H01L 29/51 (2006.01); H01L 27/11575 (2017.01); H01L 27/11524 (2017.01); H01L 27/11556 (2017.01); H01L 27/11573 (2017.01); H01L 29/792 (2006.01);
U.S. Cl.
CPC ...
H01L 27/11582 (2013.01); H01L 27/11524 (2013.01); H01L 27/11556 (2013.01); H01L 27/11573 (2013.01); H01L 27/11575 (2013.01); H01L 29/42348 (2013.01); H01L 29/511 (2013.01); H01L 29/517 (2013.01); H01L 29/792 (2013.01);
Abstract
A vertical memory device and method of manufacture thereof are provided. The vertical memory device includes gate electrode layers stacked on a substrate; a channel layer penetrating through the gate electrode layers; and a first epitaxial layer in contact with a lower portion of the channel layer and including a region having a diameter smaller than an external diameter of the channel layer.