The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 28, 2020

Filed:

May. 03, 2019
Applicant:

Intel Corporation, Santa Clara, CA (US);

Inventors:

Paul A. Nyhus, Portland, OR (US);

Mohit K. Haran, Hillsboro, OR (US);

Charles H. Wallace, Portland, OR (US);

Robert M. Bigwood, Hillsboro, OR (US);

Deepak S. Rao, Portland, OR (US);

Alexander F. Kaplan, Portland, OR (US);

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/522 (2006.01); H01L 21/768 (2006.01); H01L 21/033 (2006.01); H01L 21/311 (2006.01);
U.S. Cl.
CPC ...
H01L 21/76816 (2013.01); H01L 21/0337 (2013.01); H01L 21/31144 (2013.01); H01L 21/76811 (2013.01); H01L 21/76897 (2013.01); H01L 21/76877 (2013.01); H01L 23/5226 (2013.01);
Abstract

Via CD control for BEOL interconnects is described. For example, a method of fabricating an interconnect structure includes forming a lower metallization layer comprising alternating metal lines and dielectric lines above a substrate. The method also includes forming an inter-layer dielectric layer above the metallization layer. The method also includes forming a first grating pattern above the inter-layer dielectric layer, orthogonal to the alternating metal lines and dielectric lines of the lower metallization layer. The method also includes forming a second grating pattern above the first grating pattern. The method also includes patterning the inter-layer dielectric layer using the first grating pattern and the second grating pattern to form via locations and line regions in the inter-layer dielectric layer. The method also includes forming metal vias and metal lines in the via locations and line regions, respectively, of the inter-layer dielectric layer.


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