The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 21, 2020

Filed:

Aug. 19, 2019
Applicant:

Skyworks Solutions, Inc., Woburn, MA (US);

Inventors:

Hailing Wang, Acton, MA (US);

Dylan Charles Bartle, Arlington, MA (US);

Hanching Fuh, Allston, MA (US);

Jerod F. Mason, Bedford, MA (US);

David Scott Whitefield, Andover, MA (US);

Paul T. DiCarlo, Marlborough, MA (US);

Assignee:

SKYWORKS SOLUTIONS, INC., Woburn, MA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03K 17/16 (2006.01); H01L 23/66 (2006.01); H01L 27/12 (2006.01); H03K 17/10 (2006.01); H03K 17/693 (2006.01); H03K 17/12 (2006.01); H04B 1/38 (2015.01);
U.S. Cl.
CPC ...
H03K 17/161 (2013.01); H01L 23/66 (2013.01); H01L 27/1203 (2013.01); H03K 17/102 (2013.01); H03K 17/122 (2013.01); H03K 17/693 (2013.01); H01L 2223/6677 (2013.01); H03K 2217/0018 (2013.01); H04B 1/38 (2013.01);
Abstract

Disclosed herein are switching or other active FET configurations that implement a segmented main-auxiliary branch design. Such designs include a circuit assembly for performing a switching function that includes a branch including a plurality of main-auxiliary pairs coupled in series, wherein each main-auxiliary pair includes a main field-effect transistor (FET) in parallel with an auxiliary FET. The circuit assembly also includes a gate bias network connected to the main FETs and configured to bias the main FETs in a strong inversion region. The circuit assembly also includes an auxiliary bias network connected to the auxiliary FETs and configured to bias the auxiliary FETs in a weak inversion region.


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