The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Apr. 14, 2020
Filed:
Aug. 03, 2018
Applicant:
Tokyo Electron Limited, Tokyo, JP;
Inventors:
Joshua Hooge, Austin, TX (US);
Nathan Ip, Austin, TX (US);
Joel Estrella, Austin, TX (US);
Anton Devilliers, Albany, NY (US);
Assignee:
Tokyo Electron Limited, Tokyo, JP;
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/67 (2006.01); H01L 21/66 (2006.01); G06F 17/50 (2006.01); G06T 7/00 (2017.01);
U.S. Cl.
CPC ...
H01L 21/67288 (2013.01); G06F 17/5009 (2013.01); G06F 17/5018 (2013.01); H01L 22/20 (2013.01); G06T 7/0004 (2013.01); G06T 2207/30148 (2013.01); H01L 22/12 (2013.01);
Abstract
Disclosed herein is a technology related to the amelioration (e.g., correction) of global wafer distortion based on a determination of localized distortions of a semiconductor wafer. Herein, a distortion is either an out-of-plane distortion (OPD) or in-plane distortion (IPD). The reference plane for this distortion is based on the plane shared by the surface of a presumptively flat semiconductor wafer. This Abstract is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims.