The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 14, 2020

Filed:

Oct. 23, 2018
Applicant:

Intel Corporation, Santa Clara, CA (US);

Inventors:

Varsha Regulapati, Folsom, CA (US);

Heonwook Kim, San Jose, CA (US);

Aliasgar S. Madraswala, Folsom, CA (US);

Naga Kiranmayee Upadhyayula, Olympia, WA (US);

Purval S. Sule, Folsom, CA (US);

Jong Tai Park, Pleasanton, CA (US);

Sriram Balasubrahmanyam, Folsom, CA (US);

Manjiri M. Katmore, Santa Clara, CA (US);

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 29/00 (2006.01); G11C 29/02 (2006.01); G06F 12/02 (2006.01); G11C 16/04 (2006.01); G06F 13/16 (2006.01); G11C 16/32 (2006.01); G11C 16/20 (2006.01);
U.S. Cl.
CPC ...
G11C 29/023 (2013.01); G06F 12/0246 (2013.01); G06F 13/1668 (2013.01); G11C 16/0483 (2013.01); G11C 16/20 (2013.01); G11C 16/32 (2013.01); G11C 29/02 (2013.01); G11C 29/028 (2013.01);
Abstract

In connection with data pin timing calibration with a strobe signal, examples provide for determination of pass/fail status of a pin from multiple pass/fail results in a single operation. Determination of pass/fail results for multiple pins based on multiple applied trim offsets can be made in parallel. Accordingly, a time to determine pass/fail results from multiple trim values for a pin can be reduced, which can enable faster power-up of NAND flash devices.


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