Multi-pump memory system access circuits for sequentially executing parallel memory operations

Abstract

Multi-pump memory system access circuits for sequentially executing parallel memory operations in a memory system are disclosed. A memory system includes a plurality of memory bit cells in a memory array. Each memory bit cell is accessible at a corresponding memory address used by memory read and write operations. The memory system includes ports at which a memory read or a memory write operation is received from a processor in each cycle of a processor clock. To increase memory bandwidth of the memory system without increasing the number of access ports of the memory array within the memory system, a double-pump memory system access circuit double-pumps (i.e., time-multiplexes) the access ports of memory array, effectively doubling the number of ports of the memory array. The double-pump memory system access circuit performs sequential accesses to a port of a memory cell in a memory array within a processor clock period.