The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 07, 2020

Filed:

Jan. 23, 2018
Applicant:

Qualcomm Incorporated, San Diego, CA (US);

Inventors:

Xia Li, San Diego, CA (US);

Seung Hyuk Kang, San Diego, CA (US);

Bin Yang, San Diego, CA (US);

Gengming Tao, San Diego, CA (US);

Assignee:

QUALCOMM Incorporated, San Diego, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H04L 9/32 (2006.01); G06F 11/10 (2006.01); G11C 29/52 (2006.01); G06F 3/06 (2006.01); G11C 13/00 (2006.01); G06F 21/31 (2013.01); G11C 7/24 (2006.01); G11C 7/02 (2006.01); G11C 7/12 (2006.01); H04L 9/08 (2006.01); G06F 21/73 (2013.01); G11C 11/412 (2006.01); G11C 11/419 (2006.01);
U.S. Cl.
CPC ...
H04L 9/3278 (2013.01); G06F 3/06 (2013.01); G06F 11/1068 (2013.01); G06F 21/31 (2013.01); G06F 21/73 (2013.01); G11C 7/02 (2013.01); G11C 7/12 (2013.01); G11C 7/24 (2013.01); G11C 11/412 (2013.01); G11C 11/419 (2013.01); G11C 13/004 (2013.01); G11C 29/52 (2013.01); H04L 9/0866 (2013.01); H04L 2209/12 (2013.01); H04L 2209/805 (2013.01);
Abstract

In certain aspects, an apparatus comprises a plurality of PUF cells. Each PUF cell comprises a first transistor in series with a first loading resistive component and coupled to a common cross-coupled node and cross-coupled to a complementary common cross-coupled node, a second transistor in series with a second loading resistive component and coupled to the complementary common cross-coupled node and cross-coupled to the common cross-coupled node, a first pass-gate and a second pass-gate coupled to a bit line and the complementary bit line, respectively. The apparatus further comprises an auxiliary peripheral circuit coupled to the bit line, the complementary bit line, the common cross-coupled node, and the complementary common cross-coupled node. During activation, the selected PUF cell, together with the auxiliary peripheral circuit, forms a cross-coupled inverter pair and outputs a physical unclonable function value.


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