The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Mar. 31, 2020
Filed:
Dec. 21, 2016
Applicant:
Soitec, Bernin, FR;
Inventors:
Marcel Broekaart, Theys, FR;
Thierry Barge, Chevrieres, FR;
Pascal Guenard, Froges, FR;
Ionut Radu, Crolles, FR;
Eric Desbonnets, Lumbin, FR;
Oleg Kononchuk, Theys, FR;
Assignee:
Soitec, Bernin, FR;
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03H 3/10 (2006.01); H03H 9/13 (2006.01); H03H 9/145 (2006.01); H03H 9/17 (2006.01); H03H 9/25 (2006.01); H03H 9/56 (2006.01); H03H 9/64 (2006.01); H01L 27/20 (2006.01); H01L 41/047 (2006.01); H03H 9/02 (2006.01); H01L 41/312 (2013.01); H03H 3/02 (2006.01); H03H 3/04 (2006.01); H01L 41/335 (2013.01);
U.S. Cl.
CPC ...
H03H 9/02834 (2013.01); H01L 27/20 (2013.01); H01L 41/047 (2013.01); H01L 41/312 (2013.01); H03H 3/02 (2013.01); H03H 3/04 (2013.01); H03H 3/10 (2013.01); H03H 9/02102 (2013.01); H03H 9/02574 (2013.01); H03H 9/13 (2013.01); H03H 9/145 (2013.01); H03H 9/17 (2013.01); H03H 9/25 (2013.01); H03H 9/56 (2013.01); H03H 9/6489 (2013.01); H01L 41/335 (2013.01); H03H 2003/0407 (2013.01);
Abstract
A substrate for a surface acoustic wave device or bulk acoustic wave device, comprising a support substrate and an piezoelectric layer on the support substrate, wherein the support substrate comprises a semiconductor layer on a stiffening substrate having a coefficient of thermal expansion that is closer to the coefficient of thermal expansion of the material of the piezoelectric layer than that of silicon, the semiconductor layer being arranged between the piezoelectric layer and the stiffening substrate.