The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 31, 2020

Filed:

Sep. 20, 2018
Applicant:

Silicon Storage Technology, Inc., San Jose, CA (US);

Inventors:

Jeng-Wei Yang, Zhubei, TW;

Chun-Ming Chen, New Taipei, TW;

Man-Tang Wu, Xinpu Township, TW;

Chen-Chih Fan, Hsinchu County, TW;

Nhan Do, Saratoga, CA (US);

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/423 (2006.01); H01L 29/08 (2006.01); H01L 29/66 (2006.01); H01L 21/28 (2006.01); H01L 21/02 (2006.01); H01L 21/027 (2006.01); H01L 21/3105 (2006.01); H01L 21/762 (2006.01); H01L 21/265 (2006.01); H01L 27/11546 (2017.01); H01L 27/11521 (2017.01);
U.S. Cl.
CPC ...
H01L 29/42328 (2013.01); H01L 27/11521 (2013.01); H01L 27/11546 (2013.01); H01L 29/0847 (2013.01); H01L 29/40114 (2019.08); H01L 29/665 (2013.01); H01L 29/6653 (2013.01); H01L 29/6656 (2013.01); H01L 29/66825 (2013.01); H01L 21/0217 (2013.01); H01L 21/0274 (2013.01); H01L 21/02164 (2013.01); H01L 21/02236 (2013.01); H01L 21/26513 (2013.01); H01L 21/31053 (2013.01); H01L 21/76224 (2013.01);
Abstract

A method of forming a memory device with memory cells in a memory area, and logic devices in first and second peripheral areas. The memory cells each include a floating gate, a word line gate and an erase gate, and each logic device includes a gate. The oxide under the word line gate is formed separately from a tunnel oxide between the floating and erase gates, and is also the gate oxide in the first peripheral area. The word line gates, erase gates and gates in both peripheral areas are formed from the same polysilicon layer. The oxide between the erase gate and a source region is thicker than the tunnel oxide, which is thicker than the oxide under the word line gate.


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