The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 31, 2020

Filed:

Nov. 07, 2018
Applicant:

Micron Technology, Inc., Boise, ID (US);

Inventors:

Scott J. Derner, Boise, ID (US);

Michael Amiel Shore, Boise, ID (US);

Assignee:

Micron Technology, Inc., Boise, ID (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 27/108 (2006.01); G11C 11/403 (2006.01); H01L 27/07 (2006.01); H01L 49/02 (2006.01); H01L 29/78 (2006.01); G11C 7/18 (2006.01); H01L 23/528 (2006.01); H01L 29/08 (2006.01); H01L 29/10 (2006.01);
U.S. Cl.
CPC ...
H01L 27/108 (2013.01); G11C 11/403 (2013.01); H01L 27/07 (2013.01); H01L 28/60 (2013.01); H01L 29/7827 (2013.01); G11C 7/18 (2013.01); H01L 23/528 (2013.01); H01L 29/0847 (2013.01); H01L 29/1037 (2013.01);
Abstract

Some embodiments include a memory cell having first and second transistors and first and second capacitors. The first capacitor is vertically displaced relative to the first transistor. The first capacitor has a first node electrically coupled with a source/drain region of the first transistor, a second node electrically coupled with a common plate structure, and a first capacitor dielectric material between the first and second nodes. The second capacitor is vertically displaced relative to the second transistor. The second capacitor has a third node electrically coupled with a source/drain region of the second transistor, a fourth node electrically coupled with the common plate structure, and a second capacitor dielectric material between the first and second nodes. Some embodiments include memory arrays having 2T-2C memory cells.


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