The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 31, 2020

Filed:

Aug. 13, 2018
Applicant:

United Microelectronics Corp., Hsin-Chu, TW;

Inventors:

Shu-Wei Yeh, Taichung, TW;

Chang-Hung Chen, Tainan, TW;

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 27/02 (2006.01); G11C 11/412 (2006.01); H01L 27/11 (2006.01); G11C 11/417 (2006.01); G11C 8/16 (2006.01);
U.S. Cl.
CPC ...
H01L 27/0207 (2013.01); G11C 8/16 (2013.01); G11C 11/412 (2013.01); G11C 11/417 (2013.01); H01L 27/11 (2013.01);
Abstract

The present invention provides a layout pattern of a static random access memory (SRAM), comprising at least one substrate, two SRAM units on the substrate, respectively located in a first region and a second region which is adjacent to the first region. Each of the SRAM units includes a first inverter coupled to a second inverter and configured to form a latching circuit, the first inverter includes a first pull-up transistor (PU) and a first pull-down transistor (PD), the second inverter includes a second pull-up transistor (PU) and a second pull-down transistor (PD). A dummy layer crossing the first a region and the second region, and between the PDin the first region and the PDin the second region, and a contact structure on the dummy layer, electrically connected to a voltage source Vss.


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