The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 31, 2020

Filed:

May. 08, 2018
Applicant:

Infineon Technologies Ag, Neubiberg, DE;

Inventors:

Dietrich Bonart, Bad Abbach, DE;

Bernhard Weidgans, Bernhardswald, DE;

Johann Gatterbauer, Parsberg, AT;

Thomas Gross, Sinzing, DE;

Martina Heigl, Bogen, DE;

Assignee:

Infineon Technologies AG, Neubiberg, DE;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 25/16 (2006.01); H01L 27/146 (2006.01); H01L 33/20 (2010.01); H01L 23/552 (2006.01); H01L 33/44 (2010.01); H01L 33/38 (2010.01); H01L 51/52 (2006.01); H01L 21/768 (2006.01); H01L 21/66 (2006.01); H01L 23/522 (2006.01); H01L 23/528 (2006.01); H01L 23/532 (2006.01); H01L 23/00 (2006.01); H01L 31/055 (2014.01); H01L 33/40 (2010.01); H01L 33/46 (2010.01); H01L 33/60 (2010.01); H01L 33/62 (2010.01);
U.S. Cl.
CPC ...
H01L 25/167 (2013.01); H01L 21/76834 (2013.01); H01L 21/76877 (2013.01); H01L 22/20 (2013.01); H01L 23/528 (2013.01); H01L 23/5226 (2013.01); H01L 23/53214 (2013.01); H01L 23/53228 (2013.01); H01L 23/552 (2013.01); H01L 24/03 (2013.01); H01L 24/06 (2013.01); H01L 27/14692 (2013.01); H01L 31/055 (2013.01); H01L 33/20 (2013.01); H01L 33/38 (2013.01); H01L 33/405 (2013.01); H01L 33/44 (2013.01); H01L 33/46 (2013.01); H01L 33/60 (2013.01); H01L 33/62 (2013.01); H01L 51/5271 (2013.01); H01L 2224/05144 (2013.01); H01L 2224/48227 (2013.01); H01L 2924/12041 (2013.01); H01L 2933/0058 (2013.01); H01L 2933/0066 (2013.01); Y02E 10/52 (2013.01);
Abstract

A semiconductor device includes an active region disposed in a semiconductor substrate and an uppermost metal level including metal lines, where the uppermost metal level is disposed over the semiconductor substrate. Contact pads are disposed at a major surface of the semiconductor device, where the contact pads are coupled to the metal lines in the uppermost metal level. An isolation region separates the contact pads disposed at the major surface. Adjacent contact pads are electrically isolated from one another by a portion of the isolation region. Reflective structures are disposed between the upper metal level and the contact pads, where each of the reflective structures that is directly over the active region completely overlaps an associated portion of the isolation region separating the contact pad.


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