The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 31, 2020

Filed:

Jul. 23, 2018
Applicant:

Silicon Storage Technology, Inc., San Jose, CA (US);

Inventors:

Hsuan Liang, Hsinchu, TW;

Jeng-Wei Yang, Zhubei, TW;

Man-Tang Wu, Xinpu Township, Hsinchu County, TW;

Nhan Do, Saratoga, CA (US);

Hieu Van Tran, San Jose, CA (US);

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 16/16 (2006.01); G11C 16/04 (2006.01); H01L 27/11521 (2017.01);
U.S. Cl.
CPC ...
G11C 16/16 (2013.01); G11C 16/0425 (2013.01); H01L 27/11521 (2013.01);
Abstract

A memory device with memory cells in rows and columns, word lines connecting together the control gates for the memory cell rows, bit lines electrically connecting together the drain regions for the memory cell columns, first sub source lines each electrically connecting together the source regions in one of the memory cell rows and in a first plurality of memory cell columns, second sub source lines each electrically connecting together the source regions in one of the memory cell rows and in a second plurality of memory cell columns, first and second source lines, first select transistors each connected between one of first sub source lines and the first source line, second select transistors each connected between one of second sub source lines and the second source line, and select transistor lines each connected to gates of one of the first select transistors and one of the second select transistors.


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