logo

For the Inventor, By the Inventor

The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 10600682 B1

PDFFull Text
Date of Patent:
Mar. 24, 2020

Filed:

Oct. 26, 2018

Semiconductor devices including a stair step structure, and related methods

Applicant:

Micron Technology, Inc., Boise, ID (US);

Inventors:

John B. Matovu, Boise, ID (US);

David S. Meyaard, Boise, ID (US);

Gowrisankar Damarla, Lehi, UT (US);

Sri Sai Sivakumar Vegunta, Boise, ID (US);

Kunal Shrotri, Boise, ID (US);

Shashank Saraf, Boise, ID (US);

Kevin R. Gast, Boise, ID (US);

Jivaan Kishore Jhothiraman, Boise, ID (US);

Suresh Ramarajan, Boise, ID (US);

Lifang Xu, Boise, ID (US);

Rithu K. Bhonsle, Boise, ID (US);

Rutuparna Narulkar, Boise, ID (US);

Matthew J. King, Boise, ID (US);

Assignee:

Micron Technology, Inc., Boise, ID (US);

Attorney:

TraskBritt

Primary Examiner:

Khiem D Nguyen

Int. Cl.
CPC ...
H01L 21/768 (2006.01); H01L 23/522 (2006.01); H01L 23/528 (2006.01); H01L 21/3105 (2006.01); H01L 27/11582 (2017.01); H01L 27/11556 (2017.01); H01L 27/11575 (2017.01); H01L 27/11548 (2017.01);
U.S. Cl.
CPC ...
H01L 21/76816 (2013.01); H01L 21/31051 (2013.01); H01L 21/76811 (2013.01); H01L 21/76819 (2013.01); H01L 21/76832 (2013.01); H01L 21/76877 (2013.01); H01L 23/5226 (2013.01); H01L 23/5283 (2013.01); H01L 27/11548 (2013.01); H01L 27/11556 (2013.01); H01L 27/11575 (2013.01); H01L 27/11582 (2013.01);
Abstract

A method of forming a semiconductor structure includes forming a sacrificial material over a stack comprising alternating levels of a dielectric material and another material, forming an opening through the sacrificial material and at least some of the alternating levels of the dielectric material and the another material, forming at least one oxide material in the opening and overlying surfaces of the sacrificial material, an uppermost surface of the at least one oxide material extending more distal from a surface of a substrate than an uppermost level of the dielectric material and the another material, planarizing at least a portion of the at least one oxide material to expose a portion of the sacrificial material, and removing the sacrificial material while the uppermost surface of the at least one oxide material remains more distal from the surface of the substrate than the uppermost level of the alternating levels of the dielectric material and the another material. Related methods of forming semiconductor structures and related semiconductor devices are disclosed.

Find Patent Forward Citations

Loading…