The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 24, 2020

Filed:

Dec. 20, 2018
Applicant:

Stmicroelectronics S.r.l., Agrate Brianza, IT;

Inventors:

Fabio Enrico Carlo Disegni, Spino d'adda, IT;

Cesare Torti, Pavia, IT;

Davide Manfré, Pandino, IT;

Assignee:

STMICROELECTRONICS S.R.L., Agrate Brianza (MB), IT;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 11/00 (2006.01); G11C 13/00 (2006.01); G11C 7/18 (2006.01); G06F 13/16 (2006.01); G06F 13/40 (2006.01);
U.S. Cl.
CPC ...
G11C 13/004 (2013.01); G06F 13/1668 (2013.01); G06F 13/4068 (2013.01); G11C 7/18 (2013.01); G11C 13/003 (2013.01); G11C 13/0004 (2013.01); G11C 13/0026 (2013.01); G11C 13/0028 (2013.01); G11C 2013/0042 (2013.01); G11C 2207/005 (2013.01); G11C 2213/79 (2013.01);
Abstract

A memory device including a first memory sector and a second memory sector, each of which includes a respective plurality of local bit lines, which may be selectively coupled to a plurality of main bit lines. The memory device further includes a first amplifier and a second amplifier, and a routing circuit, arranged between the main bit lines and the first and second amplifiers. The routing circuit includes: a first lower switch, arranged between a first lower main bit line and a first input of the first amplifier; a second lower switch, arranged between the first lower main bit line and a first input of the second amplifier; a first upper switch, arranged between a first upper main bit line and the first input of the first amplifier; and a second upper switch, arranged between the first upper main bit line and the first input of the second amplifier. The second inputs of the first and second amplifiers are coupled to a second lower main bit line and to a second upper main bit line, respectively.


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