The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 17, 2020

Filed:

Jul. 03, 2018
Applicant:

Nxp Usa, Inc., Austin, TX (US);

Inventors:

Jeffrey Kevin Jones, Chandler, AZ (US);

Damon G Holmes, Scottsdale, AZ (US);

Jeffrey Spencer Roberts, Tempe, AZ (US);

Darrell Glenn Hill, Chandler, AZ (US);

Assignee:

NXP USA, Inc., Austin, TX (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03F 3/68 (2006.01); H03F 3/21 (2006.01); H03F 3/193 (2006.01); H01L 29/20 (2006.01); H03F 3/24 (2006.01); H04B 1/04 (2006.01);
U.S. Cl.
CPC ...
H03F 3/211 (2013.01); H01L 29/2003 (2013.01); H03F 3/193 (2013.01); H03F 3/24 (2013.01); H03F 2203/21106 (2013.01); H04B 2001/0408 (2013.01);
Abstract

Power amplifiers such as multi-path power amplifiers, systems employing such amplifiers, and methods of implementing amplifiers and amplifier systems are disclosed herein. In one example embodiment, a multi-path power amplifier includes a first semiconductor die with an integrated first transistor having a first source-to-drain pitch, and a second semiconductor die with an integrated second transistor having a second source-to-drain pitch, where the second source-to-drain pitch is smaller than the first source-to-drain pitch by at least 30 percent. In another example embodiment, a Doherty amplifier system includes a first semiconductor die with a first physical die area to total gate periphery ratio, and a second semiconductor die with a second physical die area to total gate periphery ratio, where the second physical die area to total gate periphery ratio is smaller than the first physical die area to total gate periphery ratio by at least 30 percent.


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