The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Mar. 17, 2020
Filed:
Sep. 12, 2018
Applicant:
Globalfoundries Inc., Grand Cayman, KY;
Inventors:
Assignee:
GLOBALFOUNDRIES INC., Grand Cayman, KY;
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/78 (2006.01); H01L 27/092 (2006.01); H03K 19/0948 (2006.01); H01L 21/762 (2006.01); H01L 29/423 (2006.01); H01L 21/8238 (2006.01); H01L 29/06 (2006.01); H01L 27/088 (2006.01); H01L 27/02 (2006.01);
U.S. Cl.
CPC ...
H01L 27/0928 (2013.01); H01L 21/7624 (2013.01); H01L 21/823892 (2013.01); H01L 27/0203 (2013.01); H01L 27/088 (2013.01); H01L 29/0649 (2013.01); H01L 29/0684 (2013.01); H01L 29/42356 (2013.01); H01L 29/7827 (2013.01); H01L 29/7831 (2013.01); H03K 19/0948 (2013.01);
Abstract
Structures for field-effect transistors and methods for fabricating a structure for field-effect transistors. A logic cell includes first and second field-effect transistors and a well defining a back gate that is arranged beneath the first and second field-effect transistors. A dielectric layer is arranged between the well and the logic cell. A plurality of deep trench isolation regions extend through the dielectric layer and are arranged to surround the first and second field-effect transistors and the well. The back gate is shared by the first and second field-effect transistors.