The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 17, 2020

Filed:

Apr. 27, 2018
Applicants:

Rahul Agarwal, Livermore, CA (US);

Milind S. Bhagavat, Los Altos, CA (US);

Priyal Shah, San Jose, CA (US);

Inventors:

Rahul Agarwal, Livermore, CA (US);

Milind S. Bhagavat, Los Altos, CA (US);

Priyal Shah, San Jose, CA (US);

Assignee:

Advanced Micro Devices, Inc., Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/522 (2006.01); H01L 23/00 (2006.01); H01L 23/31 (2006.01); H01L 21/56 (2006.01);
U.S. Cl.
CPC ...
H01L 23/5226 (2013.01); H01L 21/565 (2013.01); H01L 21/568 (2013.01); H01L 23/3157 (2013.01); H01L 24/17 (2013.01); H01L 2224/02373 (2013.01); H01L 2224/02379 (2013.01); H01L 2924/3511 (2013.01);
Abstract

Various fan-out devices are disclosed. In one aspect, a semiconductor chip device is provided that includes a redistribution layer (RDL) structure. The RDL structure includes plural metallization layers and plural polymer layers. One of the polymer layers is positioned over one of the metallization layers. The one of the metallization layers has conductor traces. The one of the polymer layers has an upper surface that is substantially planar at least where the conductor traces are positioned. A semiconductor chip is positioned on and electrically connected to the RDL structure. A molding layer is positioned on the RDL structure and at least partially encases the semiconductor chip.


Find Patent Forward Citations

Agarwal, Rahul. (2020). Fan-out package with multi-layer redistribution layer structure (U.S. Patent No. 10593620). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/10593620

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

Loading…