Sleek serial interface for a wrapper boundary register (device and method)

Abstract

Invention achieves reduced amount of terminals to control a test mode, test function and test results of a given standard for at least one 'wrapped core' () (a coresurrounded by a wrapper boundary register () as 'wrapper chain'). Test flexibility and speed of testing the core () are also improved. Suggested serial test interface comprises a state machine () and an instruction register () for wrapper-instructions, supplied through a single physical data input terminal (). The state machine () reads wrapper-instructions held by the instruction register () and generates on-chip wrapper control signals () of the given standard for the wrapper boundary register () of the core (). At least one wrapper-instruction read from the Instruction Register () provides at least one wrapper control signal (). The single input terminal () also supplies an input test signal SDI for coupling to the wrapper boundary register () as on chip logical input test signal WSI. A single output terminal () returns an output test signal SDO from an output WSO of the wrapper boundary register (). Invention may apply to IEEE 1500 control signals.