The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 10, 2020

Filed:

Jun. 12, 2019
Applicant:

Intel Corporation, Santa Clara, CA (US);

Inventors:

Gary Wallichs, San Jose, CA (US);

Sean Atsatt, San Jose, CA (US);

Assignee:

Intel Corporation, San Jose, CA (US);

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H03K 19/177 (2020.01); H03K 19/00 (2006.01); H03K 19/17736 (2020.01); H03K 19/1776 (2020.01); H03K 19/17704 (2020.01);
U.S. Cl.
CPC ...
H03K 19/17736 (2013.01); H03K 19/0008 (2013.01); H03K 19/1776 (2013.01); H03K 19/17704 (2013.01);
Abstract

Circuitry is provided that includes programmable fabric with fine-grain routing wires and a separate programmable coarse-grain routing network that provides enhanced bandwidth, low latency, and deterministic routing behavior. The programmable coarse-grain routing network may be implemented on an active interposer die. The programmable fabric may be implemented on a top die that is stacked on the active interposer die. A protocol-based network on chip (NoC) may be overlaid on the coarse-grain routing network. Although the NoC protocol is nondeterministic, the coarse-grain routing network includes an array of programmable switch boxes linked together using a predetermined number of routing channels to provide deterministic routing. Pipeline registers may be interposed within the routing channels at fixed locations to guarantee timing closure.


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