The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 10, 2020

Filed:

Apr. 25, 2018
Applicants:

Semiconductor Manufacturing International (Shanghai) Corporation, Shanghai, CN;

Semiconductor Manufacturing International (Beijing) Corporation, Beijing, CN;

Inventors:

Fang Yuan Xiao, Shanghai, CN;

Jing Yong Huang, Shanghai, CN;

Hai Yang Zhang, Shanghai, CN;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 21/762 (2006.01); H01L 29/66 (2006.01); H01L 29/78 (2006.01); H01L 27/088 (2006.01); H01L 21/8234 (2006.01); H01L 29/06 (2006.01);
U.S. Cl.
CPC ...
H01L 21/76224 (2013.01); H01L 21/823431 (2013.01); H01L 21/823481 (2013.01); H01L 27/0886 (2013.01); H01L 29/0653 (2013.01); H01L 29/66795 (2013.01); H01L 29/785 (2013.01); H01L 29/7851 (2013.01);
Abstract

A semiconductor device manufacturing method is presented. The method entails providing a semiconductor structure comprising a substrate, one or more semiconductor fins on the substrate, and a trench isolation structure around each semiconductor fin, wherein the trench isolation structure comprises a first component intersecting an extension direction of the semiconductor fin and a second component parallel with the extension direction; etching the trench isolation structure to expose a portion of the semiconductor fin; forming a patterned buffer layer on the semiconductor structure covering the second component and having an opening exposing the first component; forming an insulation layer in the opening, with upper surfaces of the insulation layer and the semiconductor fin substantially on the same horizontal level; and removing the buffer layer. This inventive concept reduces, if not eliminates, oxide loss in Single Diffusion Break (SDB) region.


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