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The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 10585825 B1

PDFFull Text
Date of Patent:
Mar. 10, 2020

Filed:

Mar. 29, 2019

Procedures for implementing source based routing within an interconnect fabric on a system on chip

Applicant:

Provino Technologies, Inc., Santa Clara, CA (US);

Inventors:

Shailendra Desai, Ahmedabad, IN;

Robert Totte, San Jose, CA (US);

Juan Sierra, San Jose, CA (US);

Parimal Gaikwad, Sunnyvale, CA (US);

Amit Jain, Ahmedabad, IN;

Mark Pearce, San Francisco, CA (US);

Assignee:

PROVINO TECHNOLOGIES, INC., Santa Clara, CA (US);

Attorney:

Beyer Law Group LLP

Primary Examiner:

Raymond N Phan

Int. Cl.
CPC ...
G06F 13/20 (2006.01); G06F 9/46 (2006.01); G06F 9/48 (2006.01); G06F 13/362 (2006.01); G06F 13/366 (2006.01); G06F 9/54 (2006.01); G06F 13/40 (2006.01); G06F 15/78 (2006.01);
U.S. Cl.
CPC ...
G06F 13/20 (2013.01); G06F 9/466 (2013.01); G06F 9/4881 (2013.01); G06F 9/542 (2013.01); G06F 13/366 (2013.01); G06F 13/3625 (2013.01); G06F 13/4022 (2013.01); G06F 15/7807 (2013.01); G06F 2213/0024 (2013.01); G06F 2213/0062 (2013.01);
Abstract

Optimizing transaction traffic on a System on a Chip (SoC) by using procedures such as expanding transactions and consolidating responses at nodes of an interconnect fabric for broadcasts, multi-casts, any-casts, source based routing type transactions, intra-streaming two or more transactions over a stream defined by a paired virtual channel-transaction class, trunking physical resources sharing common logical identifier, and using hashing to select among multiple physical resources sharing a common logical identifier.

Find Patent Forward Citations

Desai, Shailendra. (2020). Procedures for implementing source based routing within an interconnect fabric on a system on chip (U.S. Patent No. 10585825). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/10585825

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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